The standby power consumption of integrated chips used in control systems is an important consideration for systems that operate in a low power standby mode. However, as the size of transistors used in integrated chips continues to shrink, leakage currents increase and drive up standby power consumption. In the latest high performance micro-controllers, designed in technology nodes of 90 nm and below, the standby power consumption of a transistor device is dominated by leakage currents, especially at higher temperatures.
Leakage current is the current that flows between the source and the drain of a transistor device when the gate of the transistor is turned off. Typically, when the gate of a transistor is turned off a negligible amount of leakage current flows between the source and drain terminals. However, in state of the art integrated chips the minimum allowable gate length, and therefore the physical distance between source and drain, has shrunk to such a small size that even when a transistor is turned off the leakage current causes a micro-controller to still draw a significant amount of power.
Circuitries and techniques that have been implemented to address the issue of leakage current are increasingly complicated. For example, one prior art technique eliminates leakage current during standby operation by turning off power to a micro-controller using a periodic sleep-wake-up mechanism, which switches off a micro-controller and wakes it up periodically. The average energy/current consumption of such a micro-controller is calculated based upon the power consumption of the sleep-wake-up logic, plus the power consumed to switch on/off the micro, plus the power consumption during operation. Despite such efforts, the average energy consumption does not meet the stringent requirements of low power micro-controllers.